1G MRS - Efficient Redundant Switch IP Core Solution
Function Overview:
The 1G MRS (Managed Redundant Switch IP core) is a combination of SoC-e HSR-PRP switch (HPS) and Managed Ethernet Switch (MES) IP cores designed for industrial applications. It features automatic MAC learning, VLAN support, QoS management, and support for multiple redundancy protocols (e.g., HSR, PRP, RSTP, MRP, etc.) to ensure high reliability and security for high-speed data transmission. The MRS IP cores are available in a variety of Xilinx FPGA families (e.g., 7-Series, Ultrascale, Versal, etc.). Using Xilinx Vivado tools, users can quickly configure and deploy the IP core to optimize network performance and improve overall system stability and scalability, making it an ideal solution for modern industrial automation, transportation, energy, and other fields.
Description
connector
- Full-duplex 10/100/1000 Mbps Ethernet interface
- Half-duplex 10/100 Mbps Ethernet Interface
- Full-duplex 10 Gbps Ethernet interface (under development)
- Configurable 3 to 16 Ethernet ports
- MII/GMII/RGMII/SGMII/QSGMII Physical Layer Device (PHY) Interface
- Each port supports different data rates
- Copper and Fiber Media Interface: 10/100/1000Base-T, 100Base-FX, 1000Base-X
exchange
- Dynamic MAC table with automatic MAC address learning and aging (up to 2048 entries)
- Static MAC table (up to 2048 entries)
- Giant Frame Management
- Exchange based on the ethernet
- Entrance Port Mirror
- Broadcast/Multicast Storm Protection
- Rate limiting per port (broadcast, multicast and unicast traffic)
Time Synchronization
- IEEE 1588v2 stateless transparent clock function (P2P-Layer 2/E2E-Layer 2)
configure
- MDIO, UART, AXI4-Lite or CoE (Configuration over Ethernet) management interface
- Configuration over Ethernet (COE): full access to internal registers via the same Ethernet link to the CPU
- Drivers are provided with the purchase of IP cores
Distribution management
- Multicast Frame Filtering: Allows user-defined frame forwarding to specific ports based on port masks.
- Port-based VLAN support: Provides VLAN management functionality.
- Quality of Service (QoS): Optimize network traffic by prioritizing (PCP-802.1p, DSCP TOS, Ethertype).
- IEEE 802.1X EAPOL Hardware Processing: Supports hardware processing for enhanced network security.
- DSA (Decentralized Switching Architecture) Marking：
- Use the hardware features of the switch label to insert the label.
- Specifies the port from which the frame comes.
- Explain the reason for forwarding this frame.
- Manage CPU-initiated traffic and send it to specific ports.
Redundant Agreements
- RSTP (requires software stack)
- Hardware Support for RSTP
- Reference RSTP stack for Linux included with the IP core.
- Provides Posix-compatible RSTP stacks
- MRP (no software stack)
- Ring Manager (MRM)
- Ring Client (MRC)
- DLR (no software stack required)
- Beacon based nodes
- Supervisor Node
- HSR (no software stack)
- Version 3.0 (latest)
- PRP (no software stack)
- Version 3.0 (latest)
- Supports multiple HSR modes
- Supported PRP Modes: Repeat Discard, Repeat Receive
- Managed Switch IP Core Block Diagrams -
MRS IP cores available for Xilinx Vivado tools
MRS can be easily integrated into your FPGA designs by utilizing the new Xilinx Vivado tool, which allows IP cores to be used in a graphical user interface and IP parameters to be configured in an easy way.
The following Xilinx FPGA families support MRS:
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
- Versal ACAP
