1G MTSN Switch IP Core - Multi-Port TSN Time Sensitive Networking Solution
Function Overview:
The 1G MTSN Switch IP Core is a multi-port solution designed for Time Sensitive Networks (TSN), supporting 10/100/1000 Mbps Ethernet rates and providing up to 32 Ethernet ports. By supporting IEEE 802.1 series standards such as AS, Qav, Qbv, etc., the IP Core can be flexibly configured for efficient data transfer and synchronization. It supports the Xilinx FPGA family for broadcast storm protection, VLAN support and time synchronization applications, providing a complete solution for industrial automation and network control systems.
Description
connector
- Full-duplex 10/100/1000 Mbps Ethernet interface
- Configurable up to32Individual Ethernet Ports
- MII/RMII/GMII/RGMII/SGMII/QSGMII Physical Device (PHY) Interface
- Each port supports different data rates
exchange
- Dynamic MAC table with automatic MAC address learning and aging (up to 4096 entries)
- Static MAC table (up to 4096 entries)
- Giant Frame Management
- Broadcast/Multicast Storm Protection
- Rate limiting per port (broadcast, multicast and unicast traffic)
- Port-based VLAN support
Low Level Configuration
- MDIO, UART, AXI4-lite or CoE management interface.
- Configuration over Ethernet (CoE): full access to internal registers via the same Ethernet link to the CPU
- Driver provided with purchase of IP Core
Advanced Configuration
- Onboard UltraScale™FPGA for high-speed network switching and PTP time stamping
- Multi-core CPU unit supporting autonomous software applications
Time Sensitive Networks
- IEEE 802.1AS（rev）For time synchronization layer
- IEEE 802.1QavUsed to reserve flow
- Credit-based shaper: Configurable bandwidth reservations for each traffic class
- IEEE 802.1QbvTraffic for Programs
- Time-aware shaper: configurable number of timeslots
- IEEE 802.1QccFor network management
- NETCONF is used to manage YANG data.
- IEEE 802.1QciFor data process filtering and monitoring
- IEEE 802.1ABFor LLDP (Link Layer Probing Protocol)
- IEEE 802.1wFor rapid generation of tree agreements
- IEEE 802.1sFor multiple spanning tree protocols
- IEEE 802.1CBFor frame duplication and reliability elimination (*)
- For synchronized scheduling of flowsfeedthroughSupport (*)
- IEEE 802.1Qbu/802.3brFor frame grabbing (*)
Supported Xilinx FPGA Evaluation Boards
Our MTSN IP cores can be deployed in the following Xilinx families. You can find the different Xilinx product sheets and selection guides in the links below:
- 7 Series(Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale(Kintex, Virtex)
- Ultrascale+(Zynq MPSoC, Kintex, Virtex)
- Versal ACAP
In addition, we develop systems or network modules on network modules. In this case, we offer our customers who need an all-in-one solution to introduce time-sensitive networks in their equipmentMTSNKit solutions.
