IRIG-B Slave IP Core: Highly Accurate Time Synchronization Solution
Function Overview:
IRIGtimeS is a highly efficient and flexible time synchronization slave IP core designed for compliance with the IRIG 200-04 standard. The IP core supports all IRIG-B encoding algorithms, including DCLS and AM modulation, and is capable of handling seconds, minutes, hours, days and years in time code. The built-in 64-bit internal timer enables sub-microsecond synchronization with IRIG-B masters and provides accurate second and nanosecond timestamps. IRIGtimeS supports multiple Xilinx FPGA families, including 7-Series, Ultrascale, Ultrascale+, and Versal, and can be easily integrated into the Xilinx It can be easily integrated into Xilinx Vivado tools for a wide range of FPGA design projects that require precise time synchronization. The IP cores are designed for autonomy and ease of operation, and provide periodic pulse outputs for test and time synchronization applications.
Description
IRIGtimeS An IRIG 200-04 compatible time synchronization slave has been implemented on an FPGA device. The IRIG-B slave IP core has been designed to support all IRIG-B encoding algorithms as well as DCLS and AM modulation to provide maximum flexibility.
This IRIG-B slave IP core receives IRIG-B frames per second and obtains time information (seconds, minutes, hours, days, years, control functions, and binary continuous seconds) based on IRIG-B time code. The IP implements a 64-bit internal timer to provide time stamps (in seconds) and nanosecond values. The timer values and frequencies are synchronized with the received IRIG-B time information. The IP is designed to provide autonomous operation, requiring as little configuration as possible.
Supported Xilinx FPGA families:
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
- Versal
IRIGtimeS can be easily integrated into FPGA designs by integrating it with the managed Ethernet switch IP core of the Xilinx Vivado tool, which allows the IP core to be used in a graphical user interface and IP parameters to be configured in an easy way.
IRIGtimeS Key Features:
- IRIG 200-04 compliant time synchronization slave
- Supports DCLS and AM modulation
- Supports all IRIG-B encoded algorithms including year information, control functions and linear binary seconds.
- Sub-microsecond synchronization with IRIG-B masters
- 64-bit internal timer synchronized with IRIG-B master in time and frequency
- 32-bit time stamp in seconds and 32-bit time stamp in nanoseconds
- Periodic Pulse Output for Testing
