IEEE 1588v2 CPU-less Clock Synchronization Solution - 1588 Tiny IP Core
Function Overview:
1588 TinyIt is a specializedXilinx FPGAdesignerIEEE 1588-2008 V2Slave hardware clock synchronizationIPKernel. It provides accurate time stamping and clock synchronization without relying on embedded processors or general-purpose Ethernet.MACThe system is designed to provide high efficiency for resource-constrained equipment.IEEE 1588function support. TheIPThe kernel supports a variety of Ethernet interfaces, includingMII、GMII、SGMIIetc., and can handlePTPThe report supports both single- and dual-port modes. It also supports a variety of profiles (such asIEC 61850(for example, power setup files, etc.), for7-Series、Ultrascale、Ultrascale+及Versal ACAP等Xilinx FPGASeries.1588 Tiny與Xilinx VivadoTools are seamlessly integrated, making them easy to configure and integrate into theFPGAThe design ensures that theFPGAHighly accurate hardware time synchronization is performed internally.
Description
1588 Tiny The 1588 Tiny is an IEEE1588-2008 V2 slave-only hardware-compatible clock synchronization IP core for Xilinx FPGAs. It is focused on devices that require basic IEEE 1588 functionality with minimal resources. 1588 Tiny accurately timestamps IEEE 1588 messages and provides synchronized clocks using only hardware modules.
There is no need for an embedded processor and no need for a generic Ethernet MAC.1588 Tiny Includes optimized Ethernet MAC, handles PTP frames, and supports power profiles and IEC 61850, as well as other profiles.
Supported Xilinx FPGA families:
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
- Versal ACAP
The 1588 Tiny integrates with Xilinx Vivado tools to allow easy configuration of the IP core in a graphical user interface.
1588 Tiny Key Features:
General:
- For Vivado (IP integrator)
- Supports single and dual port modes
Interface:
- MII/RMII/GMII/RGMII/SGMII/QSGMII/USXGMII Physical Device (PHY) Interface
- Supports AXI-Stream interface
- Supports 10/100/1000Mbps speeds
Time synchronization:
- Supports Layer 2 PTP (single and dual port)
- Supports Layer 3 PTP (single port)
- Supported profiles: power profiles, utility profiles, IEC61850 profiles and default profiles.
- Available output timers: “64-bit nanoseconds” or “48-bit seconds + 32-bit nanoseconds”.”
- Provide PPS output
- Optional IRIG-B master output synchronized with PTP internal timer (DCLS and AM modulation)
- Support Event Timestamp
- Support Alarm Detection
