10G TSN Switch IP Core - Multi-Port Ethernet Time-Sensitive Network Solution
Generate an optimized TSN bridge or endpoint device for your application.
Honghong's new10G TSN Ethernet switch IP nucleus isThe latest version of the MTSN Switch IP core. It is also a flexible HDL code that can generate TSN endpoints or TSN bridge implementations, but optionally with a10G portsAs with other SoC-e IP cores, the IP has a rich set of common parameters for optimal functional resource tradeoffs. Like other SoC-e IP cores, this IP has a rich set of generalized parameters for optimal functional resource tradeoffs. These generalizations can also be configured graphically through the Vivado GUI.
Description
connector
- full duplex100M/1G/2.5G/5G/10GEthernet interface
- Configurable up to32Individual Ethernet Ports
- MII/RMII/GMII/RGMII/SGMII/QSGMII/USXGMII Physical layer device (PHY) interface. (For others, please contact us)
- Each port supports different data rates
exchange
- AutomaticMACDynamics of Address Learning and AgingMAC表
- StaticMAC表
- Giant Frame Management
- broadcasting/Multicast Storm Protection
- Rate limiting per port (broadcast, multicast and unicast traffic)
- port-basedVLANsupport sth.
- Low Level Configuration
Low Level Configuration
- MDIO、UART、AXI4-liteManagement Interface.
- PurchaseIPNucleus provides drivers
Advanced Configuration
- NETCONF YANGModel Support (CNC(Configuration)
- Advanced ConfigurationGUI
Time Sensitive Networks
- IEEE 802.1AS（rev(for time synchronization layer)
- IEEE 802.1QavUsed to reserve flow
- Credit-based shaper: Configurable bandwidth reservations for each traffic class
- IEEE 802.1QbvFor Program Flow
- Time-aware shaper: configurable number of timeslots
- IEEE 802.1QccFor network management
- NETCONFfor managingYANGData
- IEEE 802.1QciFor data flow filtering and monitoring (*）
- IEEE 802.1ABused forLLDP(Link Layer Discovery Protocol)
- IEEE 802.1wQuickly Generate a Tree Agreement
- IEEE 802.1sMultiple Spanning Tree Protocol
- IEEE 802.1CBFrame Duplication and Reliability Elimination (*）
- IEEE 802.1Qbu/802.3brFrame grabbing (*）
- *Future versions or interoperability testing to be determined
Supported Xilinx FPGA Evaluation Boards
MacroHong 10G MTSN IP cores can be deployed in the following Xilinx families. You can find the different Xilinx product sheets and selection guides in the links below:
● 7 Series(Zynq, Spartan, Artix, Kintex, Virtex)
:: Ultrascale(Kintex, Virtex)
:: Ultrascale+(Zynq MPSoC, Kintex, Virtex)
:: Versal ACAP
在Evaluation BoardIn addition, we have introducedSystem level modules( SoM ), availableSoC-e 的 IP Preloaded design of the coreSoC-e can provide SoMs based on the 7 series, Ultrascale or Ultrascale+ Xilinx FPGA families.
