IRIGtimeM: IRIG-B\u4e3b\u7ad9IP\u6838<\/title>\r\n <style>\r\n \/* \u9650\u5236\u6a23\u5f0f\u50c5\u4f5c\u7528\u65bc\u9019\u500b\u5340\u584a *\/\r\n .content-section {\r\n font-family: 'Segoe UI', Tahoma, Geneva, Verdana, sans-serif;\r\n background-color: #fff;\r\n color: #333;\r\n padding: 20px;\r\n }\r\n .content-section h1, .content-section h2 {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section h1 {\r\n font-size: 28px;\r\n text-align: center;\r\n margin-bottom: 20px;\r\n border-bottom: 2px solid #27317e;\r\n padding-bottom: 10px;\r\n }\r\n .content-section h2 {\r\n font-size: 22px;\r\n margin-top: 30px;\r\n margin-bottom: 10px;\r\n border-left: 4px solid #27317e;\r\n padding-left: 10px;\r\n }\r\n .content-section p, .content-section ul {\r\n font-size: 16px;\r\n line-height: 1.8;\r\n }\r\n .content-section ul {\r\n margin-top: 10px;\r\n padding-left: 20px;\r\n }\r\n .content-section li {\r\n margin-bottom: 10px;\r\n list-style-type: none;\r\n }\r\n .content-section li::before {\r\n content: '\u25b8 ';\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section .highlight {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n <\/style>\r\n<\/head>\r\n<body>\r\n <div class=\"content-section\">\r\n\r\n <p><span class=\"highlight\">IRIGtimeM<\/span> An IRIG 200-04 compatible time synchronization master has been implemented on an FPGA device. This IRIG-B master IP is designed to support all IRIG-B encoding algorithms as well as DCLS and AM modulation to provide maximum flexibility.<\/p>\r\n\r\n <p>This IRIG-B master IP generates IRIG-B frames per second, including mandatory and optional time information (seconds, minutes, hours, days, years, control functions, and consecutive binary seconds), depending on the IRIG-B time code selected on the configuration. The IP is capable of supporting autonomous operation without excessive configuration.<\/p>\r\n\r\n <h2>Supported Xilinx FPGA families:<\/h2>\r\n <ul>\r\n <li>7-Series (Zynq SoC, Spartan, Artix, Kintex, Virtex)<\/li>\r\n <li>Ultrascale (Kintex, Virtex)<\/li>\r\n <li>Ultrascale+ (Zynq MPSoC, Kintex, Virtex)<\/li>\r\n <li>Versal ACAP<\/li>\r\n <\/ul>\r\n\r\n <p>IRIGtimeM can be easily integrated into FPGA designs by integrating it with the managed Ethernet switch IP core of the Xilinx Vivado tool, which allows the IP core to be used in a graphical user interface and IP parameters to be configured in an easy way.<\/p>\r\n\r\n <h2>IRIGtimeM Key Features:<\/h2>\r\n <ul>\r\n <li>IRIG 200-04 compliant time synchronization masters<\/li>\r\n <li>Supports DCLS and AM modulation<\/li>\r\n <li>Supports all IRIG-B encoded algorithms, including year information, control functions and continuous binary seconds.<\/li>\r\n <li>Output type (IRIG-B time code) can be configured before implementation and during operation<\/li>\r\n <li>Precision IRIG-B output for nanosecond accuracy<\/li>\r\n <li>32-bit timestamp input for initial IP settings<\/li>\r\n <li>Periodic pulse output for testing<\/li>\r\n <\/ul>\r\n <\/div>\r\n<\/body>\r\n<\/html>\r\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>","protected":false},"excerpt":{"rendered":"<h3>Function Overview:<\/h3>\n<p>IRIGtimeM is an IRIG-B master IP core designed for the Xilinx FPGA family and is fully compatible with the IRIG 200-04 standard. The IP core supports all IRIG-B encoding algorithms and is flexible enough to handle DCLS and AM modulation with up to nanosecond accuracy. IRIGtimeM generates IRIG-B frames with complete time information, including seconds, minutes, hours, days, years, and control functions. Easily integrated into FPGA designs through Xilinx Vivado tools, the IP core provides flexible configuration options and accurate time synchronization for a wide range of applications.<\/p>","protected":false},"featured_media":47699,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_eb_attr":"","ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"default","ocean_disable_heading":"default","ocean_post_title":"","ocean_post_subheading":"","ocean_post_title_style":"","ocean_post_title_background_color":"","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"default","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","iawp_total_views":5},"product_brand":[],"product_cat":[2016],"product_tag":[2879,2878,2848,2840,2877,2874,2876,2843,2875,2880],"class_list":{"0":"post-47779","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-wireless-communication","7":"product_tag-am","8":"product_tag-dcls","9":"product_tag-fpga","10":"product_tag-ip-core","11":"product_tag-irig-200-04","12":"product_tag-irig-b","13":"product_tag-irigtimem","14":"product_tag-xilinx-fpga","15":"product_tag-2875","16":"product_tag-2880","18":"entry","19":"has-media","21":"first","22":"instock","23":"shipping-taxable","24":"product-type-simple","25":"has-product-nav","26":"col","27":"span_1_of_4","28":"owp-content-center","29":"owp-thumbs-layout-horizontal","30":"owp-btn-normal","31":"owp-tabs-layout-horizontal","32":"has-no-thumbnails"},"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47779","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/types\/product"}],"replies":[{"embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/comments?post=47779"}],"version-history":[{"count":6,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47779\/revisions"}],"predecessor-version":[{"id":47812,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47779\/revisions\/47812"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/media\/47699"}],"wp:attachment":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/media?parent=47779"}],"wp:term":[{"taxonomy":"product_brand","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_brand?post=47779"},{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_cat?post=47779"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_tag?post=47779"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}

\n\t\t\t\t\t\t

\n\t\t\t\t\t

\n\t\t\t

\n\t\t\t\t\t\t

\n\t\t\t\t

\n\t\t\t\t\t\r\n\r\n\r\n \r\n \r\n IRIGtimeM: IRIG-B\u4e3b\u7ad9IP\u6838<\/title>\r\n <style>\r\n \/* \u9650\u5236\u6a23\u5f0f\u50c5\u4f5c\u7528\u65bc\u9019\u500b\u5340\u584a *\/\r\n .content-section {\r\n font-family: 'Segoe UI', Tahoma, Geneva, Verdana, sans-serif;\r\n background-color: #fff;\r\n color: #333;\r\n padding: 20px;\r\n }\r\n .content-section h1, .content-section h2 {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section h1 {\r\n font-size: 28px;\r\n text-align: center;\r\n margin-bottom: 20px;\r\n border-bottom: 2px solid #27317e;\r\n padding-bottom: 10px;\r\n }\r\n .content-section h2 {\r\n font-size: 22px;\r\n margin-top: 30px;\r\n margin-bottom: 10px;\r\n border-left: 4px solid #27317e;\r\n padding-left: 10px;\r\n }\r\n .content-section p, .content-section ul {\r\n font-size: 16px;\r\n line-height: 1.8;\r\n }\r\n .content-section ul {\r\n margin-top: 10px;\r\n padding-left: 20px;\r\n }\r\n .content-section li {\r\n margin-bottom: 10px;\r\n list-style-type: none;\r\n }\r\n .content-section li::before {\r\n content: '\u25b8 ';\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section .highlight {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n <\/style>\r\n<\/head>\r\n<body>\r\n <div class=\"content-section\">\r\n\r\n <p><span class=\"highlight\">IRIGtimeM<\/span> An IRIG 200-04 compatible time synchronization master has been implemented on an FPGA device. This IRIG-B master IP is designed to support all IRIG-B encoding algorithms as well as DCLS and AM modulation to provide maximum flexibility.<\/p>\r\n\r\n <p>This IRIG-B master IP generates IRIG-B frames per second, including mandatory and optional time information (seconds, minutes, hours, days, years, control functions, and consecutive binary seconds), depending on the IRIG-B time code selected on the configuration. The IP is capable of supporting autonomous operation without excessive configuration.<\/p>\r\n\r\n <h2>Supported Xilinx FPGA families:<\/h2>\r\n <ul>\r\n <li>7-Series (Zynq SoC, Spartan, Artix, Kintex, Virtex)<\/li>\r\n <li>Ultrascale (Kintex, Virtex)<\/li>\r\n <li>Ultrascale+ (Zynq MPSoC, Kintex, Virtex)<\/li>\r\n <li>Versal ACAP<\/li>\r\n <\/ul>\r\n\r\n <p>IRIGtimeM can be easily integrated into FPGA designs by integrating it with the managed Ethernet switch IP core of the Xilinx Vivado tool, which allows the IP core to be used in a graphical user interface and IP parameters to be configured in an easy way.<\/p>\r\n\r\n <h2>IRIGtimeM Key Features:<\/h2>\r\n <ul>\r\n <li>IRIG 200-04 compliant time synchronization masters<\/li>\r\n <li>Supports DCLS and AM modulation<\/li>\r\n <li>Supports all IRIG-B encoded algorithms, including year information, control functions and continuous binary seconds.<\/li>\r\n <li>Output type (IRIG-B time code) can be configured before implementation and during operation<\/li>\r\n <li>Precision IRIG-B output for nanosecond accuracy<\/li>\r\n <li>32-bit timestamp input for initial IP settings<\/li>\r\n <li>Periodic pulse output for testing<\/li>\r\n <\/ul>\r\n <\/div>\r\n<\/body>\r\n<\/html>\r\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>","protected":false},"excerpt":{"rendered":"<h3>Function Overview:<\/h3>\n<p>IRIGtimeM is an IRIG-B master IP core designed for the Xilinx FPGA family and is fully compatible with the IRIG 200-04 standard. The IP core supports all IRIG-B encoding algorithms and is flexible enough to handle DCLS and AM modulation with up to nanosecond accuracy. IRIGtimeM generates IRIG-B frames with complete time information, including seconds, minutes, hours, days, years, and control functions. Easily integrated into FPGA designs through Xilinx Vivado tools, the IP core provides flexible configuration options and accurate time synchronization for a wide range of applications.<\/p>","protected":false},"featured_media":47699,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_eb_attr":"","ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"default","ocean_disable_heading":"default","ocean_post_title":"","ocean_post_subheading":"","ocean_post_title_style":"","ocean_post_title_background_color":"","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"default","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","iawp_total_views":5},"product_brand":[],"product_cat":[2016],"product_tag":[2879,2878,2848,2840,2877,2874,2876,2843,2875,2880],"class_list":{"0":"post-47779","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-wireless-communication","7":"product_tag-am","8":"product_tag-dcls","9":"product_tag-fpga","10":"product_tag-ip-core","11":"product_tag-irig-200-04","12":"product_tag-irig-b","13":"product_tag-irigtimem","14":"product_tag-xilinx-fpga","15":"product_tag-2875","16":"product_tag-2880","18":"entry","19":"has-media","21":"first","22":"instock","23":"shipping-taxable","24":"product-type-simple","25":"has-product-nav","26":"col","27":"span_1_of_4","28":"owp-content-center","29":"owp-thumbs-layout-horizontal","30":"owp-btn-normal","31":"owp-tabs-layout-horizontal","32":"has-no-thumbnails"},"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47779","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/types\/product"}],"replies":[{"embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/comments?post=47779"}],"version-history":[{"count":6,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47779\/revisions"}],"predecessor-version":[{"id":47812,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47779\/revisions\/47812"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/media\/47699"}],"wp:attachment":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/media?parent=47779"}],"wp:term":[{"taxonomy":"product_brand","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_brand?post=47779"},{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_cat?post=47779"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_tag?post=47779"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}