IEEE 1588v2 \u7121CPU\u5f9e\u7ad9\u6642\u9418<\/title>\r\n <style>\r\n \/* \u9650\u5236\u6a23\u5f0f\u50c5\u4f5c\u7528\u65bc\u9019\u500b\u5340\u584a *\/\r\n .content-section {\r\n font-family: 'Segoe UI', Tahoma, Geneva, Verdana, sans-serif;\r\n background-color: #fff;\r\n color: #333;\r\n padding: 20px;\r\n }\r\n .content-section h1, .content-section h2 {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section h1 {\r\n font-size: 28px;\r\n text-align: center;\r\n margin-bottom: 20px;\r\n border-bottom: 2px solid #27317e;\r\n padding-bottom: 10px;\r\n }\r\n .content-section h2 {\r\n font-size: 22px;\r\n margin-top: 30px;\r\n margin-bottom: 10px;\r\n border-left: 4px solid #27317e;\r\n padding-left: 10px;\r\n }\r\n .content-section p, .content-section ul {\r\n font-size: 16px;\r\n line-height: 1.8;\r\n }\r\n .content-section ul {\r\n margin-top: 10px;\r\n padding-left: 20px;\r\n }\r\n .content-section li {\r\n margin-bottom: 10px;\r\n list-style-type: none;\r\n }\r\n .content-section li::before {\r\n content: '\u25b8 ';\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section .highlight {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n <\/style>\r\n<\/head>\r\n<body>\r\n <div class=\"content-section\">\r\n\r\n <p><span class=\"highlight\">1588 Tiny<\/span> The 1588 Tiny is an IEEE1588-2008 V2 slave-only hardware-compatible clock synchronization IP core for Xilinx FPGAs. It is focused on devices that require basic IEEE 1588 functionality with minimal resources. 1588 Tiny accurately timestamps IEEE 1588 messages and provides synchronized clocks using only hardware modules.<\/p>\r\n\r\n <p>There is no need for an embedded processor and no need for a generic Ethernet MAC.<span class=\"highlight\">1588 Tiny<\/span> Includes optimized Ethernet MAC, handles PTP frames, and supports power profiles and IEC 61850, as well as other profiles.<\/p>\r\n\r\n <h2>Supported Xilinx FPGA families:<\/h2>\r\n <ul>\r\n <li>7-Series (Zynq, Spartan, Artix, Kintex, Virtex)<\/li>\r\n <li>Ultrascale (Kintex, Virtex)<\/li>\r\n <li>Ultrascale+ (Zynq MPSoC, Kintex, Virtex)<\/li>\r\n <li>Versal ACAP<\/li>\r\n <\/ul>\r\n\r\n <p>The 1588 Tiny integrates with Xilinx Vivado tools to allow easy configuration of the IP core in a graphical user interface.<\/p>\r\n\r\n <h2>1588 Tiny Key Features:<\/h2>\r\n <h3>General:<\/h3>\r\n <ul>\r\n <li>For Vivado (IP integrator)<\/li>\r\n <li>Supports single and dual port modes<\/li>\r\n <\/ul>\r\n\r\n <h3>Interface:<\/h3>\r\n <ul>\r\n <li>MII\/RMII\/GMII\/RGMII\/SGMII\/QSGMII\/USXGMII Physical Device (PHY) Interface<\/li>\r\n <li>Supports AXI-Stream interface<\/li>\r\n <li>Supports 10\/100\/1000Mbps speeds<\/li>\r\n <\/ul>\r\n\r\n <h3>Time synchronization:<\/h3>\r\n <ul>\r\n <li>Supports Layer 2 PTP (single and dual port)<\/li>\r\n <li>Supports Layer 3 PTP (single port)<\/li>\r\n <li>Supported profiles: power profiles, utility profiles, IEC61850 profiles and default profiles.<\/li>\r\n <li>Available output timers: \u201c64-bit nanoseconds\u201d or \u201c48-bit seconds + 32-bit nanoseconds\u201d.\u201d<\/li>\r\n <li>Provide PPS output<\/li>\r\n <li>Optional IRIG-B master output synchronized with PTP internal timer (DCLS and AM modulation)<\/li>\r\n <li>Support Event Timestamp<\/li>\r\n <li>Support Alarm Detection<\/li>\r\n <\/ul>\r\n\r\n <\/div>\r\n<\/body>\r\n<\/html>\r\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>","protected":false},"excerpt":{"rendered":"<h3>Function Overview:<\/h3>\n<p><span lang=\"EN-US\">1588 Tiny<\/span>It is a specialized<span lang=\"EN-US\">Xilinx FPGA<\/span>designer<span lang=\"EN-US\">IEEE 1588-2008 V2<\/span>Slave hardware clock synchronization<span lang=\"EN-US\">IP<\/span>Kernel. It provides accurate time stamping and clock synchronization without relying on embedded processors or general-purpose Ethernet.<span lang=\"EN-US\">MAC<\/span>The system is designed to provide high efficiency for resource-constrained equipment.<span lang=\"EN-US\">IEEE 1588<\/span>function support. The<span lang=\"EN-US\">IP<\/span>The kernel supports a variety of Ethernet interfaces, including<span lang=\"EN-US\">MII<\/span>\u3001<span lang=\"EN-US\">GMII<\/span>\u3001<span lang=\"EN-US\">SGMII<\/span>etc., and can handle<span lang=\"EN-US\">PTP<\/span>The report supports both single- and dual-port modes. It also supports a variety of profiles (such as<span lang=\"EN-US\">IEC 61850<\/span>(for example, power setup files, etc.), for<span lang=\"EN-US\">7-Series<\/span>\u3001<span lang=\"EN-US\">Ultrascale<\/span>\u3001<span lang=\"EN-US\">Ultrascale+<\/span>\u53ca<span lang=\"EN-US\">Versal ACAP<\/span>\u7b49<span lang=\"EN-US\">Xilinx FPGA<\/span>Series.<span lang=\"EN-US\">1588 Tiny<\/span>\u8207<span lang=\"EN-US\">Xilinx Vivado<\/span>Tools are seamlessly integrated, making them easy to configure and integrate into the<span lang=\"EN-US\">FPGA<\/span>The design ensures that the<span lang=\"EN-US\">FPGA<\/span>Highly accurate hardware time synchronization is performed internally.<\/p>","protected":false},"featured_media":47701,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_eb_attr":"","ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"default","ocean_disable_heading":"default","ocean_post_title":"","ocean_post_subheading":"","ocean_post_title_style":"","ocean_post_title_background_color":"","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"default","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","iawp_total_views":68},"product_brand":[],"product_cat":[2016],"product_tag":[2868,2869,2867,2840,2871,2872,2843,2873,2870],"class_list":{"0":"post-47769","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-wireless-communication","7":"product_tag-1588-tiny","8":"product_tag-fpga","9":"product_tag-ieee-1588v2","10":"product_tag-ip-core","11":"product_tag-ptp","12":"product_tag-vivado","13":"product_tag-xilinx-fpga","14":"product_tag-2873","15":"product_tag-2870","17":"entry","18":"has-media","20":"first","21":"instock","22":"shipping-taxable","23":"product-type-simple","24":"has-product-nav","25":"col","26":"span_1_of_4","27":"owp-content-center","28":"owp-thumbs-layout-horizontal","29":"owp-btn-normal","30":"owp-tabs-layout-horizontal","31":"has-no-thumbnails"},"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47769","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/types\/product"}],"replies":[{"embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/comments?post=47769"}],"version-history":[{"count":9,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47769\/revisions"}],"predecessor-version":[{"id":47810,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47769\/revisions\/47810"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/media\/47701"}],"wp:attachment":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/media?parent=47769"}],"wp:term":[{"taxonomy":"product_brand","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_brand?post=47769"},{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_cat?post=47769"},{"taxon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\n\t\t\t\t\t\r\n\r\n\r\n \r\n \r\n IEEE 1588v2 \u7121CPU\u5f9e\u7ad9\u6642\u9418<\/title>\r\n <style>\r\n \/* \u9650\u5236\u6a23\u5f0f\u50c5\u4f5c\u7528\u65bc\u9019\u500b\u5340\u584a *\/\r\n .content-section {\r\n font-family: 'Segoe UI', Tahoma, Geneva, Verdana, sans-serif;\r\n background-color: #fff;\r\n color: #333;\r\n padding: 20px;\r\n }\r\n .content-section h1, .content-section h2 {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section h1 {\r\n font-size: 28px;\r\n text-align: center;\r\n margin-bottom: 20px;\r\n border-bottom: 2px solid #27317e;\r\n padding-bottom: 10px;\r\n }\r\n .content-section h2 {\r\n font-size: 22px;\r\n margin-top: 30px;\r\n margin-bottom: 10px;\r\n border-left: 4px solid #27317e;\r\n padding-left: 10px;\r\n }\r\n .content-section p, .content-section ul {\r\n font-size: 16px;\r\n line-height: 1.8;\r\n }\r\n .content-section ul {\r\n margin-top: 10px;\r\n padding-left: 20px;\r\n }\r\n .content-section li {\r\n margin-bottom: 10px;\r\n list-style-type: none;\r\n }\r\n .content-section li::before {\r\n content: '\u25b8 ';\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section .highlight {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n <\/style>\r\n<\/head>\r\n<body>\r\n <div class=\"content-section\">\r\n\r\n <p><span class=\"highlight\">1588 Tiny<\/span> The 1588 Tiny is an IEEE1588-2008 V2 slave-only hardware-compatible clock synchronization IP core for Xilinx FPGAs. It is focused on devices that require basic IEEE 1588 functionality with minimal resources. 1588 Tiny accurately timestamps IEEE 1588 messages and provides synchronized clocks using only hardware modules.<\/p>\r\n\r\n <p>There is no need for an embedded processor and no need for a generic Ethernet MAC.<span class=\"highlight\">1588 Tiny<\/span> Includes optimized Ethernet MAC, handles PTP frames, and supports power profiles and IEC 61850, as well as other profiles.<\/p>\r\n\r\n <h2>Supported Xilinx FPGA families:<\/h2>\r\n <ul>\r\n <li>7-Series (Zynq, Spartan, Artix, Kintex, Virtex)<\/li>\r\n <li>Ultrascale (Kintex, Virtex)<\/li>\r\n <li>Ultrascale+ (Zynq MPSoC, Kintex, Virtex)<\/li>\r\n <li>Versal ACAP<\/li>\r\n <\/ul>\r\n\r\n <p>The 1588 Tiny integrates with Xilinx Vivado tools to allow easy configuration of the IP core in a graphical user interface.<\/p>\r\n\r\n <h2>1588 Tiny Key Features:<\/h2>\r\n <h3>General:<\/h3>\r\n <ul>\r\n <li>For Vivado (IP integrator)<\/li>\r\n <li>Supports single and dual port modes<\/li>\r\n <\/ul>\r\n\r\n <h3>Interface:<\/h3>\r\n <ul>\r\n <li>MII\/RMII\/GMII\/RGMII\/SGMII\/QSGMII\/USXGMII Physical Device (PHY) Interface<\/li>\r\n <li>Supports AXI-Stream interface<\/li>\r\n <li>Supports 10\/100\/1000Mbps speeds<\/li>\r\n <\/ul>\r\n\r\n <h3>Time synchronization:<\/h3>\r\n <ul>\r\n <li>Supports Layer 2 PTP (single and dual port)<\/li>\r\n <li>Supports Layer 3 PTP (single port)<\/li>\r\n <li>Supported profiles: power profiles, utility profiles, IEC61850 profiles and default profiles.<\/li>\r\n <li>Available output timers: \u201c64-bit nanoseconds\u201d or \u201c48-bit seconds + 32-bit nanoseconds\u201d.\u201d<\/li>\r\n <li>Provide PPS output<\/li>\r\n <li>Optional IRIG-B master output synchronized with PTP internal timer (DCLS and AM modulation)<\/li>\r\n <li>Support Event Timestamp<\/li>\r\n <li>Support Alarm Detection<\/li>\r\n <\/ul>\r\n\r\n <\/div>\r\n<\/body>\r\n<\/html>\r\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>","protected":false},"excerpt":{"rendered":"<h3>Function Overview:<\/h3>\n<p><span lang=\"EN-US\">1588 Tiny<\/span>It is a specialized<span lang=\"EN-US\">Xilinx FPGA<\/span>designer<span lang=\"EN-US\">IEEE 1588-2008 V2<\/span>Slave hardware clock synchronization<span lang=\"EN-US\">IP<\/span>Kernel. It provides accurate time stamping and clock synchronization without relying on embedded processors or general-purpose Ethernet.<span lang=\"EN-US\">MAC<\/span>The system is designed to provide high efficiency for resource-constrained equipment.<span lang=\"EN-US\">IEEE 1588<\/span>function support. The<span lang=\"EN-US\">IP<\/span>The kernel supports a variety of Ethernet interfaces, including<span lang=\"EN-US\">MII<\/span>\u3001<span lang=\"EN-US\">GMII<\/span>\u3001<span lang=\"EN-US\">SGMII<\/span>etc., and can handle<span lang=\"EN-US\">PTP<\/span>The report supports both single- and dual-port modes. It also supports a variety of profiles (such as<span lang=\"EN-US\">IEC 61850<\/span>(for example, power setup files, etc.), for<span lang=\"EN-US\">7-Series<\/span>\u3001<span lang=\"EN-US\">Ultrascale<\/span>\u3001<span lang=\"EN-US\">Ultrascale+<\/span>\u53ca<span lang=\"EN-US\">Versal ACAP<\/span>\u7b49<span lang=\"EN-US\">Xilinx FPGA<\/span>Series.<span lang=\"EN-US\">1588 Tiny<\/span>\u8207<span lang=\"EN-US\">Xilinx Vivado<\/span>Tools are seamlessly integrated, making them easy to configure and integrate into the<span lang=\"EN-US\">FPGA<\/span>The design ensures that the<span lang=\"EN-US\">FPGA<\/span>Highly accurate hardware time synchronization is performed internally.<\/p>","protected":false},"featured_media":47701,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_eb_attr":"","ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"default","ocean_disable_heading":"default","ocean_post_title":"","ocean_post_subheading":"","ocean_post_title_style":"","ocean_post_title_background_color":"","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"default","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","iawp_total_views":68},"product_brand":[],"product_cat":[2016],"product_tag":[2868,2869,2867,2840,2871,2872,2843,2873,2870],"class_list":{"0":"post-47769","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-wireless-communication","7":"product_tag-1588-tiny","8":"product_tag-fpga","9":"product_tag-ieee-1588v2","10":"product_tag-ip-core","11":"product_tag-ptp","12":"product_tag-vivado","13":"product_tag-xilinx-fpga","14":"product_tag-2873","15":"product_tag-2870","17":"entry","18":"has-media","20":"first","21":"instock","22":"shipping-taxable","23":"product-type-simple","24":"has-product-nav","25":"col","26":"span_1_of_4","27":"owp-content-center","28":"owp-thumbs-layout-horizontal","29":"owp-btn-normal","30":"owp-tabs-layout-horizontal","31":"has-no-thumbnails"},"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47769","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/types\/product"}],"replies":[{"embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/comments?post=47769"}],"version-history":[{"count":9,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47769\/revisions"}],"predecessor-version":[{"id":47810,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product\/47769\/revisions\/47810"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/media\/47701"}],"wp:attachment":[{"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/media?parent=47769"}],"wp:term":[{"taxonomy":"product_brand","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_brand?post=47769"},{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/hongtronics.com\/en\/wp-json\/wp\/v2\/product_cat?post=47769"},{"taxon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