\u7cbe\u78ba\u6642\u9593\u57fa\u790eIP Core: IEEE1588v2\u666e\u901a\u548c\u908a\u754c\u6642\u9418<\/title>\r\n <style>\r\n \/* \u9650\u5236\u6a23\u5f0f\u50c5\u4f5c\u7528\u65bc\u9019\u500b\u5340\u584a *\/\r\n .content-section {\r\n font-family: 'Segoe UI', Tahoma, Geneva, Verdana, sans-serif;\r\n background-color: #fff;\r\n color: #333;\r\n padding: 20px;\r\n }\r\n .content-section h1, .content-section h2 {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section h1 {\r\n font-size: 28px;\r\n text-align: center;\r\n margin-bottom: 20px;\r\n border-bottom: 2px solid #27317e;\r\n padding-bottom: 10px;\r\n }\r\n .content-section h2 {\r\n font-size: 22px;\r\n margin-top: 30px;\r\n margin-bottom: 10px;\r\n border-left: 4px solid #27317e;\r\n padding-left: 10px;\r\n }\r\n .content-section p, .content-section ul {\r\n font-size: 16px;\r\n line-height: 1.8;\r\n }\r\n .content-section ul {\r\n margin-top: 10px;\r\n padding-left: 20px;\r\n }\r\n .content-section li {\r\n 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class=\"highlight\">\u786c\u9ad4\u6642\u9593\u6233\u8a18\u55ae\u5143\uff08TSU\uff09<\/span>\uff1a\u80fd\u5920\u6e96\u78ba\u5730\u70baIEEE 1588\u4e8b\u4ef6\u6d88\u606f\u52a0\u6642\u9593\u6233\u8a18\uff0c\u4e26\u63d0\u4f9b\u5177\u6709\u4e9e\u5fae\u79d2\u7cbe\u5ea6\u7684\u53ef\u8abf\u8a08\u6642\u5668\u3002TSU\u6709\u5169\u7a2e\u7248\u672c\uff1aPTB TSU\u548cPTBLite TSU\u3002<\/li>\r\n <li><span class=\"highlight\">PTB TSU<\/span>\uff1a\u8a2d\u8a08\u70ba\u9023\u63a5\u5230MAC\u548cPHY\u4e4b\u9593\u7684\u4ecb\u8cea\u7368\u7acb\u4ecb\u9762\uff08[G] MII\uff09\uff0c\u89e3\u6790\u6240\u6709\u4e59\u592a\u7db2\u5e40\u4e26\u6aa2\u67e5\u54ea\u4e9b\u662fIEEE 1588\u3002<\/li>\r\n <li><span class=\"highlight\">PTBLite TSU<\/span>\uff1a\u5229\u7528Zynq GMAC\u4e2d\u7684PTP\u89e3\u6790\u5668\uff0c\u4ee5\u8f03\u5c11\u7684FPGA\u8cc7\u6e90\u63d0\u4f9bTSU\uff0c\u4f46\u6709\u4e00\u4e9b\u9650\u5236\u3002<\/li>\r\n <li>\u5169\u7a2e\u7248\u672c\u7684TSU\u90fd\u53ef\u4ee5\u4f7f\u7528\u5167\u90e8\u53ef\u8abf\u8a08\u6642\u5668\u6216\u5f9e\u53e6\u4e00\u500bTSU\u7372\u53d6\u8a08\u6642\u5668\u503c\uff0c\u5141\u8a31\u591a\u500b\u4e59\u592a\u7db2\u9023\u63a5\u5171\u7528\u540c\u4e00\u8a08\u6642\u5668\u3002<\/li>\r\n <\/ul>\r\n\r\n <h2>\u8edf\u9ad4PTP\u53c3\u8003\u8a2d\u8a08\uff1a<\/h2>\r\n <p>SoC-e\u63d0\u4f9b\u4e86Linux\u5167\u6838\u88dc\u4e01\uff0c\u5141\u8a31\u4f7f\u7528Linux PTP\u786c\u9ad4\u6642\u9418\uff08PHC\uff09\u5b50\u7cfb\u7d71\u8a2a\u554fTSU\u3002\u6b64\u5916\uff0c\u9084\u6709\u958b\u6e90LinuxPTP\u8edf\u9ad4\u5806\u758a\u7684\u4fee\u6539\u7248\u672c\uff0c\u6a21\u7d44\u5316\u8a2d\u8a08\u6613\u65bc\u79fb\u690d\u3002<\/p>\r\n\r\n <h2>\u652f\u63f4\u7684Xilinx FPGA\u7cfb\u5217\uff1a<\/h2>\r\n <ul>\r\n <li>7-Series (Zynq SoC, Spartan, Artix, Kintex, Virtex)<\/li>\r\n <li>Ultrascale (Kintex, Virtex)<\/li>\r\n <li>Ultrascale+ (Zynq MPSoC, Kintex, Virtex)<\/li>\r\n <li>Versal ACAP<\/li>\r\n <\/ul>\r\n\r\n <p>\u900f\u904eXilinx Vivado\u5de5\u5177\uff0c\u53ef\u4ee5\u8f15\u9b06\u6574\u5408\u5230FPGA\u8a2d\u8a08\u4e2d\uff0c\u8a72\u5de5\u5177\u5141\u8a31\u5728\u5716\u5f62\u5316\u4f7f\u7528\u8005\u4ecb\u9762\u4e2d\u4f7f\u7528IP\u5167\u6838\uff0c\u4e26\u7c21\u4fbf\u914d\u7f6eIP\u53c3\u6578\u3002<\/p>\r\n\r\n <h2>\u7cbe\u78ba\u6642\u9593\u57fa\u790eIP Core\u7684\u4e3b\u8981\u529f\u80fd\uff1a<\/h2>\r\n <h3>\u786c\u9ad4\u529f\u80fd\uff1a<\/h3>\r\n <ul>\r\n <li>\u652f\u63f410\/100\/1000Mbps\/AXI-Stream\uff08\u7528\u65bc10Gbps\/25Gbps\uff09\u4ecb\u9762<\/li>\r\n <li>32\u4f4d\u79d2\/32\u4f4d\u7d0d\u79d2\u8a08\u6578\u5668<\/li>\r\n <li>32\u4f4d\u5143\u4e9e\u7d0d\u79d2\u983b\u7387\u8abf\u6574<\/li>\r\n <li>\u6bcf\u79d2\u4e00\u8108\u885d\u8f38\u51fa<\/li>\r\n <li>\u53ef\u9078\u983b\u7387\u8f38\u51fa\uff081 KHz\/2 KHz\/4 KHz\/8 KHz\/16 KHz\/32 KHz\uff09<\/li>\r\n <li>\u6700\u4f4e\u7684FPGA\u8cc7\u6e90\u5229\u7528\u7387<\/li>\r\n <li>\u8b66\u5831\u751f\u6210<\/li>\r\n <li>\u4e8b\u4ef6\u6642\u9593\u6233\u8a18\u8a18\u9304<\/li>\r\n <\/ul>\r\n\r\n <h3>\u8edf\u9ad4\u529f\u80fd\uff1a<\/h3>\r\n <ul>\r\n <li>\u666e\u901a\u6642\u9418\uff08\u4e3b\u7ad9\u548c\u5f9e\u7ad9\uff09\u64cd\u4f5c<\/li>\r\n <li>\u7aef\u5230\u7aef\u548c\u9ede\u5c0d\u9ede\u5ef6\u9072\u6a5f\u5236\u652f\u63f4<\/li>\r\n <li>\u652f\u63f4\u4e59\u592a\u7db2\uff08\u7b2c2\u5c64\uff09\u548cIPv4\uff08\u7b2c3\u5c64\uff09\u4ecb\u9762\u4e0a\u7684PTP<\/li>\r\n <li>VLAN\u652f\u6301<\/li>\r\n <li>\u53ef\u7d50\u5408HSR-PRP\u548c\u7db2\u7ba1\u4e59\u592a\u7db2IP\u5167\u6838\u4f7f\u7528<\/li>\r\n <\/ul>\r\n\r\n <h2>\u8a2d\u5b9a\u6a94\u652f\u63f4\uff1a<\/h2>\r\n <ul>\r\n <li>\u5de5\u696d\u8a2d\u5b9a\u6a94\uff1a\u9810\u8a2d\u3001\u96fb\u6e90\u3001\u96fb\u6e90\u5be6\u7528\u7a0b\u5f0fIEC 61850-9-3\u3001IEEE 802.1AS<\/li>\r\n <li>\u6c7d\u8eca\u8a2d\u5b9a\u6a94\uff1aIEEE 802.1AS\u901a\u7528PTP\uff08gPTP\uff09\u8a2d\u5b9a\u6a94<\/li>\r\n <li>\u4f01\u696d\u8a2d\u5b9a\u6a94\/5G\/\u96fb\u4fe1\u8a2d\u5b9a\u6a94\uff1aG.8265.1\uff0cG.8275.1\u548cG.8275.2<\/li>\r\n <\/ul>\r\n\r\n <p>IEEE 1588\u7cfb\u7d71\u7684\u6700\u7d42\u7cbe\u5ea6\u53d6\u6c7a\u65bc\u591a\u500b\u56e0\u7d20\uff0c\u5305\u62ec\u672c\u5730\u6642\u9418\u983b\u7387\u3001\u8cc7\u6599\u93c8\u4e2d\u7684\u6642\u9593\u6233\u8a18\u4f4d\u7f6e\u7b49\u3002\u4ee5\u4e0b\u5716\u793a\u7bc4\u5546\u696dGrandmaster\u8a2d\u5099\u548cZedboard Avnet Devopment Platfrom\u4e4b\u9593\u7684PPS\u6e2c\u91cf\u8aa4\u5dee\uff0c\u4f7f\u7528\u7cbe\u78ba\u6642\u9593\u57fa\u790e\u9032\u884c\u786c\u9ad4\u8f14\u52a9\u6642\u9593\u6233\u8a18\uff08+\/-50 ns\uff09\u3002<\/p>\r\n <\/div>\r\n<\/body>\r\n<\/html>\r\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Function Overview.<\/p>\n<p>The Precision Time Base IP Core is an IEEE1588v2-compliant clock synchronization solution for Xilinx FPGAs with hardware timestamping that achieves sub-microsecond accuracy at network speeds from 10Mbps to 25Gbps. The IP core supports synchronization of multiple Ethernet connections and performs efficient timer tuning through FPGA hardware modules for industrial automation, 5G telecom, autonomous driving and other application scenarios. Its excellent scalability and high accuracy make it ideal for time-sensitive applications. It can be integrated with Linux PTP hardware clock subsystem and supports various industrial and automotive profiles such as IEEE 802.1AS and IEC 61850-9-3.<\/p>","protected":false},"featured_media":47700,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_eb_attr":"","ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"default","ocean_disable_heading":"default","ocean_post_title":"","ocean_post_subheading":"","ocean_post_title_style":"","ocean_post_title_background_color":"","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"default","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0"},"product_brand":[],"product_cat":[2016],"product_tag":[2866,2863,2861,2865,2843,2432,2864,2862],"class_list":["post-47760","product","type-product","status-publish","has-post-thumbnail","product_cat-wireless-communication","product_tag-5g","product_tag-fpga-ip","product_tag-ieee1588v2","product_tag-ptp","product_tag-xilinx-fpga","product_tag-2432","product_tag-2864","product_tag-2862","entry","has-media","first","instock","shipping-taxable","product-type-simple","has-product-nav","col","span_1_of_4","owp-content-center","owp-thumbs-layout-horizontal","owp-btn-normal","owp-tabs-layout-horizontal","has-no-thumbnails"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t<meta 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\n\t\t\t\t\t\r\n\r\n\r\n \r\n \r\n \u7cbe\u78ba\u6642\u9593\u57fa\u790eIP Core: IEEE1588v2\u666e\u901a\u548c\u908a\u754c\u6642\u9418<\/title>\r\n <style>\r\n \/* \u9650\u5236\u6a23\u5f0f\u50c5\u4f5c\u7528\u65bc\u9019\u500b\u5340\u584a *\/\r\n .content-section {\r\n font-family: 'Segoe UI', Tahoma, Geneva, Verdana, sans-serif;\r\n background-color: #fff;\r\n color: #333;\r\n padding: 20px;\r\n }\r\n .content-section h1, .content-section h2 {\r\n color: #27317e;\r\n font-weight: bold;\r\n }\r\n .content-section h1 {\r\n font-size: 28px;\r\n text-align: center;\r\n margin-bottom: 20px;\r\n border-bottom: 2px solid #27317e;\r\n padding-bottom: 10px;\r\n }\r\n .content-section h2 {\r\n font-size: 22px;\r\n margin-top: 30px;\r\n margin-bottom: 10px;\r\n border-left: 4px solid #27317e;\r\n padding-left: 10px;\r\n }\r\n .content-section p, .content-section ul {\r\n font-size: 16px;\r\n line-height: 1.8;\r\n }\r\n .content-section ul {\r\n margin-top: 10px;\r\n padding-left: 20px;\r\n }\r\n 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class=\"highlight\">\u786c\u9ad4\u6642\u9593\u6233\u8a18\u55ae\u5143\uff08TSU\uff09<\/span>\uff1a\u80fd\u5920\u6e96\u78ba\u5730\u70baIEEE 1588\u4e8b\u4ef6\u6d88\u606f\u52a0\u6642\u9593\u6233\u8a18\uff0c\u4e26\u63d0\u4f9b\u5177\u6709\u4e9e\u5fae\u79d2\u7cbe\u5ea6\u7684\u53ef\u8abf\u8a08\u6642\u5668\u3002TSU\u6709\u5169\u7a2e\u7248\u672c\uff1aPTB TSU\u548cPTBLite TSU\u3002<\/li>\r\n <li><span class=\"highlight\">PTB TSU<\/span>\uff1a\u8a2d\u8a08\u70ba\u9023\u63a5\u5230MAC\u548cPHY\u4e4b\u9593\u7684\u4ecb\u8cea\u7368\u7acb\u4ecb\u9762\uff08[G] MII\uff09\uff0c\u89e3\u6790\u6240\u6709\u4e59\u592a\u7db2\u5e40\u4e26\u6aa2\u67e5\u54ea\u4e9b\u662fIEEE 1588\u3002<\/li>\r\n <li><span class=\"highlight\">PTBLite TSU<\/span>\uff1a\u5229\u7528Zynq GMAC\u4e2d\u7684PTP\u89e3\u6790\u5668\uff0c\u4ee5\u8f03\u5c11\u7684FPGA\u8cc7\u6e90\u63d0\u4f9bTSU\uff0c\u4f46\u6709\u4e00\u4e9b\u9650\u5236\u3002<\/li>\r\n <li>\u5169\u7a2e\u7248\u672c\u7684TSU\u90fd\u53ef\u4ee5\u4f7f\u7528\u5167\u90e8\u53ef\u8abf\u8a08\u6642\u5668\u6216\u5f9e\u53e6\u4e00\u500bTSU\u7372\u53d6\u8a08\u6642\u5668\u503c\uff0c\u5141\u8a31\u591a\u500b\u4e59\u592a\u7db2\u9023\u63a5\u5171\u7528\u540c\u4e00\u8a08\u6642\u5668\u3002<\/li>\r\n <\/ul>\r\n\r\n <h2>\u8edf\u9ad4PTP\u53c3\u8003\u8a2d\u8a08\uff1a<\/h2>\r\n <p>SoC-e\u63d0\u4f9b\u4e86Linux\u5167\u6838\u88dc\u4e01\uff0c\u5141\u8a31\u4f7f\u7528Linux PTP\u786c\u9ad4\u6642\u9418\uff08PHC\uff09\u5b50\u7cfb\u7d71\u8a2a\u554fTSU\u3002\u6b64\u5916\uff0c\u9084\u6709\u958b\u6e90LinuxPTP\u8edf\u9ad4\u5806\u758a\u7684\u4fee\u6539\u7248\u672c\uff0c\u6a21\u7d44\u5316\u8a2d\u8a08\u6613\u65bc\u79fb\u690d\u3002<\/p>\r\n\r\n <h2>\u652f\u63f4\u7684Xilinx FPGA\u7cfb\u5217\uff1a<\/h2>\r\n <ul>\r\n <li>7-Series (Zynq SoC, Spartan, Artix, Kintex, Virtex)<\/li>\r\n <li>Ultrascale (Kintex, Virtex)<\/li>\r\n <li>Ultrascale+ (Zynq MPSoC, Kintex, Virtex)<\/li>\r\n <li>Versal ACAP<\/li>\r\n <\/ul>\r\n\r\n <p>\u900f\u904eXilinx Vivado\u5de5\u5177\uff0c\u53ef\u4ee5\u8f15\u9b06\u6574\u5408\u5230FPGA\u8a2d\u8a08\u4e2d\uff0c\u8a72\u5de5\u5177\u5141\u8a31\u5728\u5716\u5f62\u5316\u4f7f\u7528\u8005\u4ecb\u9762\u4e2d\u4f7f\u7528IP\u5167\u6838\uff0c\u4e26\u7c21\u4fbf\u914d\u7f6eIP\u53c3\u6578\u3002<\/p>\r\n\r\n <h2>\u7cbe\u78ba\u6642\u9593\u57fa\u790eIP Core\u7684\u4e3b\u8981\u529f\u80fd\uff1a<\/h2>\r\n <h3>\u786c\u9ad4\u529f\u80fd\uff1a<\/h3>\r\n <ul>\r\n <li>\u652f\u63f410\/100\/1000Mbps\/AXI-Stream\uff08\u7528\u65bc10Gbps\/25Gbps\uff09\u4ecb\u9762<\/li>\r\n <li>32\u4f4d\u79d2\/32\u4f4d\u7d0d\u79d2\u8a08\u6578\u5668<\/li>\r\n <li>32\u4f4d\u5143\u4e9e\u7d0d\u79d2\u983b\u7387\u8abf\u6574<\/li>\r\n <li>\u6bcf\u79d2\u4e00\u8108\u885d\u8f38\u51fa<\/li>\r\n <li>\u53ef\u9078\u983b\u7387\u8f38\u51fa\uff081 KHz\/2 KHz\/4 KHz\/8 KHz\/16 KHz\/32 KHz\uff09<\/li>\r\n <li>\u6700\u4f4e\u7684FPGA\u8cc7\u6e90\u5229\u7528\u7387<\/li>\r\n <li>\u8b66\u5831\u751f\u6210<\/li>\r\n <li>\u4e8b\u4ef6\u6642\u9593\u6233\u8a18\u8a18\u9304<\/li>\r\n <\/ul>\r\n\r\n <h3>\u8edf\u9ad4\u529f\u80fd\uff1a<\/h3>\r\n <ul>\r\n <li>\u666e\u901a\u6642\u9418\uff08\u4e3b\u7ad9\u548c\u5f9e\u7ad9\uff09\u64cd\u4f5c<\/li>\r\n <li>\u7aef\u5230\u7aef\u548c\u9ede\u5c0d\u9ede\u5ef6\u9072\u6a5f\u5236\u652f\u63f4<\/li>\r\n <li>\u652f\u63f4\u4e59\u592a\u7db2\uff08\u7b2c2\u5c64\uff09\u548cIPv4\uff08\u7b2c3\u5c64\uff09\u4ecb\u9762\u4e0a\u7684PTP<\/li>\r\n <li>VLAN\u652f\u6301<\/li>\r\n <li>\u53ef\u7d50\u5408HSR-PRP\u548c\u7db2\u7ba1\u4e59\u592a\u7db2IP\u5167\u6838\u4f7f\u7528<\/li>\r\n <\/ul>\r\n\r\n <h2>\u8a2d\u5b9a\u6a94\u652f\u63f4\uff1a<\/h2>\r\n <ul>\r\n <li>\u5de5\u696d\u8a2d\u5b9a\u6a94\uff1a\u9810\u8a2d\u3001\u96fb\u6e90\u3001\u96fb\u6e90\u5be6\u7528\u7a0b\u5f0fIEC 61850-9-3\u3001IEEE 802.1AS<\/li>\r\n <li>\u6c7d\u8eca\u8a2d\u5b9a\u6a94\uff1aIEEE 802.1AS\u901a\u7528PTP\uff08gPTP\uff09\u8a2d\u5b9a\u6a94<\/li>\r\n <li>\u4f01\u696d\u8a2d\u5b9a\u6a94\/5G\/\u96fb\u4fe1\u8a2d\u5b9a\u6a94\uff1aG.8265.1\uff0cG.8275.1\u548cG.8275.2<\/li>\r\n <\/ul>\r\n\r\n <p>IEEE 1588\u7cfb\u7d71\u7684\u6700\u7d42\u7cbe\u5ea6\u53d6\u6c7a\u65bc\u591a\u500b\u56e0\u7d20\uff0c\u5305\u62ec\u672c\u5730\u6642\u9418\u983b\u7387\u3001\u8cc7\u6599\u93c8\u4e2d\u7684\u6642\u9593\u6233\u8a18\u4f4d\u7f6e\u7b49\u3002\u4ee5\u4e0b\u5716\u793a\u7bc4\u5546\u696dGrandmaster\u8a2d\u5099\u548cZedboard Avnet Devopment Platfrom\u4e4b\u9593\u7684PPS\u6e2c\u91cf\u8aa4\u5dee\uff0c\u4f7f\u7528\u7cbe\u78ba\u6642\u9593\u57fa\u790e\u9032\u884c\u786c\u9ad4\u8f14\u52a9\u6642\u9593\u6233\u8a18\uff08+\/-50 ns\uff09\u3002<\/p>\r\n <\/div>\r\n<\/body>\r\n<\/html>\r\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Function Overview.<\/p>\n<p>The Precision Time Base IP Core is an IEEE1588v2-compliant clock synchronization solution for Xilinx FPGAs with hardware timestamping that achieves sub-microsecond accuracy at network speeds from 10Mbps to 25Gbps. The IP core supports synchronization of multiple Ethernet connections and performs efficient timer tuning through FPGA hardware modules for industrial automation, 5G telecom, autonomous driving and other application scenarios. Its excellent scalability and high accuracy make it ideal for time-sensitive applications. It can be integrated with Linux PTP hardware clock subsystem and supports various industrial and automotive profiles such as IEEE 802.1AS and IEC 61850-9-3.<\/p>","protected":false},"featured_media":47700,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_eb_attr":"","ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"default","ocean_disable_heading":"default","ocean_post_title":"","ocean_post_subheading":"","ocean_post_title_style":"","ocean_post_title_background_color":"","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"default","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0"},"product_brand":[],"product_cat":[2016],"product_tag":[2866,2863,2861,2865,2843,2432,2864,2862],"class_list":["post-47760","product","type-product","status-publish","has-post-thumbnail","product_cat-wireless-communication","product_tag-5g","product_tag-fpga-ip","product_tag-ieee1588v2","product_tag-ptp","product_tag-xilinx-fpga","product_tag-2432","product_tag-2864","product_tag-2862","entry","has-media","first","instock","shipping-taxable","product-type-simple","has-product-nav","col","span_1_of_4","owp-content-center","owp-thumbs-layout-horizontal","owp-btn-normal","owp-tabs-layout-horizontal","has-no-thumbnails"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t<meta 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