{"id":19942,"date":"2022-04-01T09:57:29","date_gmt":"2022-04-01T01:57:29","guid":{"rendered":"https:\/\/hongtronics.com\/?p=19942"},"modified":"2024-09-18T10:50:03","modified_gmt":"2024-09-18T02:50:03","slug":"mrs-switch-ip-core","status":"publish","type":"post","link":"https:\/\/hongtronics.com\/en\/mrs-switch-ip-core\/","title":{"rendered":"Network Management + Redundant MRS Switch IP Siliconware enables redundant Ethernet functionality!"},"content":{"rendered":"
\"\"<\/figure>\n\n\n\n

Semiconductor Silicon Intelligence, also known as IP core, is a hardware description language program with circuit-specific functionality, often used in digital circuits. The program is independent of the IC process and can be ported to different semiconductor processes to produce IC wafers, thus helping developers to reduce their workload and accelerate time-to-market.<\/p>\n\n\n\n

1G Managed Redundant Switch IP Core<\/strong>- Available for Xilinx Vivado<\/h2>\n\n\n\n

The Managed Redundant Switch IP core (MRS) is a combination of the Avision HSR-PRP Switch (HPS) and Managed Ethernet Switch (MES) IP cores with redundant Ethernet switching capabilities.The MES module is a non-blocking cross-switching matrix that allows continuous transmission between all ports. It implements a store-and-forward switching methodology to fully satisfy the Ethernet standard policy about verifying the integrity of each frame before forwarding it. On the other hand, the HPS module introduces HSR and PRP redundancy in the required ports. the switching method for HSR is Cut-Through. Therefore, the combination of MES and HPS provides the highest performance and maximum compatibility with the standard.<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

Managed redundant switches can be easily integrated into a user's FPGA design with the new Xilinx Vivado tool, which allows IP cores to be used and IP parameters to be configured in a simple way within the graphical user interface.<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

The following Xilinx FPGA families can support the Avision MRS IP core:<\/p>\n\n\n\n

\u25aa 6 series (Spartan, Virtex)<\/p>\n\n\n\n

\u25aa 7 series (Zynq, Spartan, Artix, Kintex, Virtex)<\/p>\n\n\n\n

\u25aa Ultra-large (Kintex, Virtex)<\/p>\n\n\n\n

\u25aa Ultrascale+ (Zynq MPSoC, Kintex, Virtex)<\/p>\n\n\n\n

HK Network Management Redundant Switch IP Core Main Functions<\/strong><\/h2>\n\n\n\n

# Interface<\/h2>\n\n\n\n

Full-duplex 10\/100\/1000 Mbps Ethernet interface<\/p>\n\n\n\n

\u25aa Half-duplex 10\/100 Mbps Ethernet interface<\/p>\n\n\n\n

\u25aa Full-duplex 10 Gbps Ethernet interface (under development)<\/p>\n\n\n\n

\u25aa Configurable 3 to 16 Ethernet ports<\/p>\n\n\n\n

MII\/ GMII\/ RGMII\/ SGMII\/ QSGMII Physical Layer Device (PHY) interface<\/p>\n\n\n\n

Each port supports different data rates.<\/p>\n\n\n\n

\u25aa Copper and fiber media interfaces: 10\/100\/1000Base-T, 100Base-FX, 1000Base-X<\/p>\n\n\n\n

# Exchange<\/h2>\n\n\n\n

\u25aa Dynamic MAC table with automatic MAC address learning and aging (up to 2048 entries)<\/p>\n\n\n\n

\u25aa Static MAC table (up to 2048 entries)<\/p>\n\n\n\n

\u25aa Giant frame management<\/p>\n\n\n\n

Ethernet-based switching<\/p>\n\n\n\n

\u25aa Entrance port mirroring<\/p>\n\n\n\n

\u25aa Broadcast\/multicast storm protection<\/p>\n\n\n\n

\u25aa Rate limiting per port (broadcast, multicast and unicast traffic)<\/p>\n\n\n\n

# Circulation management<\/h2>\n\n\n\n

Multicast frame filtering<\/p>\n\n\n\n

\u25aa Translation port mask: user-defined frame to specific port forwarding<\/p>\n\n\n\n

\u25aa Port-based VLAN support<\/p>\n\n\n\n

\u25aa Quality of Service (QoS): priority (PCP-802.1p, DSCP TOS, Ethernet type)<\/p>\n\n\n\n

\u25aa IEEE 802.1X EAPOL hardware processing<\/p>\n\n\n\n

DSA (Distributed Switching Architecture) labeling: Ideally, Ethernet switches should support \u201cswitch labeling\u201d when using DSAs.\u201d<\/p>\n\n\n\n

# Configuration<\/h2>\n\n\n\n

\u25aa MDIO, UART, AXI4-Lite or CoE (Configuration over Ethernet) management interface<\/p>\n\n\n\n

Configuration over Ethernet (COE): full access to internal registers via the same Ethernet link to the CPU<\/p>\n\n\n\n

\u25aa Provide drivers when purchasing IP cores<\/p>\n\n\n\n

# Redundant agreements<\/h2>\n\n\n\n

\u25aa RSTP (requires software stack)<\/p>\n\n\n\n

\u25aa MRP (no software stacks)<\/p>\n\n\n\n

\u25aa DLR (no software stacks required)<\/p>\n\n\n\n

\u25aa HSR (no software stacks required)<\/p>\n\n\n\n

\u25aa PRP (no software stacks)<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n
\n\n\n\n
\"\"
Contact Us<\/figcaption><\/figure><\/div>","protected":false},"excerpt":{"rendered":"

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